Typically, modern communication systems require the generation of a stable carrier signal, for example having a desired and stable carrier frequency. Such communication systems typically employ synthesizers and the like to generate such carrier signals. Control circuitry embodying the present invention may, for example, be used to generate such carrier signals and may form part or all of such synthesizers.
The performance of today's front-end architectures for wireless communication depends to an increasing degree on the performance of the employed synthesizers. This is because new wireless communication standards that aim for high data efficiency, like IEEE 802.16e (Mobile WiMAX), set tight requirements on the clarity and agility of the carrier generation. At the same time, the increased market pressure for highly integrated solutions with growing digital complexity is moving the target technologies for such front-ends below 100 nm, which adds additional limitations to the analogue design approach for synthesizer integration. As a result, it is a challenging task to implement competitive high-performance analogue blocks in a technology optimized for high-density digital design.
Typical demands in current synthesizer design are as follows. Firstly, a large voltage controlled oscillator (VCO) range (e.g. 487 MHz) is typically desired at a frequency (e.g. 3 GHz) where parasitic effects significantly reduce the usable control range. Secondly, a 1.2-V power supply voltage (for example) is often desired, which limits the usable VCO control range to e.g. 300 mV (when considering saturation margins), which is in conflict with the requirement for low VCO gain and extended frequency control range, Thirdly, there is the desire for low power consumption, which leads to higher power-related impedances (such as VCO tank impedance and loop filter impedance), but which conflicts with the requirement for lower impedance to give low noise (e.g. −95 dBc@ 100-kHz offset).